Method and apparatus for blanking noise present in an alternating electrical signal

ABSTRACT

A noise blanking circuit for eliminating evidence of noise present in an incoming alternating electrical control signal, such as a shaft encoder or tachometer signal in a servo control circuit, is disclosed. The alternating electrical signal is input to a first input of a shift register having a plurality of outputs. Clock signals having a preselected frequency are input to a second input of the shift register for digitally sampling the alternating electrical signal at the times of occurrence of the clock signals so as to produce digital samples shiftably stored in respective storage locations of the shift register, which are connected to the plurality of outputs of the shift register. The digital samples appearing at predetermined ones of the plurality of outputs of the shift register are input to a logic circuit for producing a first logic state (low state) as an output signal, when a first logic state appears at the predetermined ones of the plurality of outputs of the shift register, and a second logic state (high state) as the output signal, when a second logic state appears at the predetermined ones of the plurality of outputs of the shift register. The selectivity of the noise blanking circuit can be selected by adjusting the clock signal frequency and/or the number of storage locations included in the shift register and/or changing the predetermined ones of the plurality of outputs of the shift register which are input to the logic circuit. Other features are also disclosed.

BACKGROUND OF THE INVENTION

This invention relates to electrical noise detection circuits and, moreparticularly, to circuits responsive to an incoming alternatingelectrical signal permeated by noise for producing an outgoingelectrical signal in which the noise is suppressed. Specifically, theinvention is directed to a method and apparatus for blanking noisepresent in an incoming alternating electrical control signal forproducing an outgoing electrical control signal in which no evidence ofthe noise appears, especially in inherently noisy environments, such asencountered in the use of servomotors in conjunction with the operationof printers, disc drives, and other equipment used in informationprocessing.

In order to facilitate an understanding of the invention, the inventionwill be described by way of example in connection with printers, namely,daisy wheel printers. The exemplary use of the invention in connectionwith a daisy wheel printer, however, is by way of illustration only andis not to be interpreted as a limitation of the principles of theinvention to daisy wheel printers or to printers generally. As willbecome clear, the principles which underlie the invention applygenerally to control circuits responsive to an incoming alternatingelectrical control signal in which noise is present for recognizingnoise and producing an outgoing electrical control signal which is freefrom noise.

In a daisy wheel printer, a petal shaped print wheel is rotatablymounted to a carriage. The carriage is reciprocally mounted with respectto a paper feeder so that the reciprocal movement of the carriage isorthogonal with respect to the direction of paper feed, for example, thepaper is fed vertically and the carriage is moved horizontally. Rotationof the print wheel, reciprocation of the carriage, and movement of thepaper by means of the paper feeder, preconditions the daisy wheelprinter for enabling a character to be printed at a preselected printposition. Printing requires that the paper be indexed to a lineposition, the carriage be moved to a character position, and the printwheel be rotated to a selected character, whereupon a hammer means isenergized for striking the wheel causing the wheel to be impacted on aribbon interposed between the wheel and the paper, thereby imprinting acharacter on the paper.

The print wheel and the carriage are moved to the appropriate positionsby respective servomechanisms. In the case of the print wheel, theservomechanism is under the control of a host which selects thecharacters to be printed. The order in which the characters are printedis also determined by the host which selects the character positions.

It is desirable that the carriage is moved to the proper characterposition and the print wheel is rotated to the proper character beforethe hammer means is energized for printing the character on the paper. Along extant problem to which the present invention is addressed is thatif the print wheel and/or carriage are not properly positioned by thetime that the hammer means is energized, the quality of the printingsuffers. That is, if there is a disparity between the position of theprint wheel and/or carriage specified by the host and the actualposition of the print wheel and/or carriage, imprecise positioningresults which causes poor registration of the character with respect toa line on the paper, only a portion of the character being printed, andother unacceptable deviant print characteristics. Furthermore, andperhaps an even more onerous problem is that imprecise positioning ofthe print wheel and/or carriage can result in damage to or breakage ofthe print wheel. If the print wheel is rotated to an imprecise positionevidenced by the petal shaped cantilevered character imprinting elementbeing offset, that is, slightly out of registration with, the hammermeans, impact of the hammer means against the character imprintingelement can damage or break the element, thereby necessitatingreplacement of the print wheel.

In view of the criticality which attaches to properly positioning theprint wheel and carriage in order to assure print quality and avoidprinter downtime, the respective servomechanisms which position theprint wheel and carriage include respective servomotors and closed loopservo control circuits responsive to a command signal from the host forcontrollably moving the print wheel and carriage to one of variouspositions with negative feedback for maintaining the position untilanother command signal is provided. Position feedback is generallyprovided by respective shaft encoder signals or can be derived fromrespective tachometer signals, and under optimum conditions the shaftencoders or tachometers must produce signals having sufficientsignal-to-noise so that proper positioning can be achieved. However,spurious noise generated by noise sources, such as alternating currentpower lines, fluorescent light fixtures, other information processingequipment, etc., in the vicinity of the daisy wheel printer, decreasesthe signal-to-noise ratio of the shaft encoder or tachometer signals.The noise problem is exacerbated by the fact that the brushes of theservomotors themselves generate electrical noise and the daisy wheelprinter has other noise sources, such as static electrical charges fromthe paper feeder. Consequently, noise is present which can adverselyaffect the signal-to-noise ratio of the signals produced by the shaftencoders or tachometers. As a result, the precision with which the printwheel and carriage are positioned can be substantially impaired.

In the past, the incoming alternating electrical control signals fromthe shaft encoders or tachometers have been filtered by analog noisefilters in the form of resistor-capacitor filters. Theseresistor-capacitor filters, however, have various disadvantages. Thetime delays associated with resistor-capacitor filters adversely affectthe response of the servo control circuits. Furthermore, the bandwidthof such resistor-capacitor filters is limited. Typically, only very highfrequency noise is filtered. If high-frequency noise is filtered,however, the high-frequency content of the signals produced by the shaftencoders or tachometers is also eliminated. This results in rounding theleading and trailing edges in the case where the signals from the shaftencoders or tachometers are rectangular pulses. Unfortunately, sharpleading and trailing edges are needed in order to assure properoperation of digital circuitry. Furthermore, adjustability of theresistor-capacitor filters requires potentiometers or variablecapacitors which are expensive.

A more advanced noise recognition and suppression technique is disclosedin a copending patent application of Tri S. Van, U.S. Ser. No. 536,916filed on Sept. 27, 1983, entitled METHOD AND APPARATUS FOR MASKING NOISEPRESENT IN AN ALTERNATING ELECTRICAL SIGNAL assigned to the sameassignee as this application. The embodiments disclosed in thereferenced copending application include a hard-wired digital circuit,as well as a microprocessor circuit implementation. Although theseembodiments produce acceptable results, the hard-wired digital circuitincludes several one shots, which can be unstable, and a number ofresistor-capacitor delay circuits. Hence, the hard-wired digital circuitis complex and can be difficult to implement. Furthermore, themicroprocessor circuit implementation must handle a significant burden,such that the capability of a single microprocessor can be insufficient,and, therefore, multiple microprocessors can be needed in order toexecute all functions required of the control circuit, which adds to thecomplexity and increases the expense of the microprocessor circuitimplementation.

The invention provides cancellation of the effects of noise present inan incoming alternating electrical control signal without thelimitations of a resistor-capacitor filter. Furthermore, the inventionprovides a noise blanking circuit which avoids the use of unstable oneshots, as well as resistor-capacitor delay circuits, present in thehard-wired digital circuit disclosed in the referenced copendingapplication and includes fewer circuit elements so as to result in aless complex circuit which can be easily implemented. Like thehard-wired digital circuit disclosed in the referenced copendingapplication, however, the invention provides a circuit which does notplace a significant demand on a microprocessor circuit and, therefore,avoids the complexity and expense of a multiple microprocessorimplementation. The method and apparatus in accordance with theinvention can effectively reduce the impact of noise present in theincoming alternating electrical control signals from the shaft encodersor tachometers included in the servo control circuits for the printwheel and carriage of a daisy wheel printer in order to increase theprecision with which the print wheel and carriage are positioned,thereby assuring print quality and avoiding damage to or breakage of thewheel.

SUMMARY OF THE INVENTION

The invention provides a method and apparatus for blanking noise whichappears in an incoming alternating electrical control signal, such asthe signal from a shaft encoder or tachometer included in a servocontrol circuit of a positioning servomechanism, for example, theservomechanisms included in a daisy wheel printer for positioning aprint wheel and carriage. The method and apparatus in accordance withthe invention for blanking noise present in an alternating electricalcontrol signal are characterized in that the evidence of noise presentin the incoming alternating electrical control signal is eliminatedwithout reducing the frequency content of the signal, thereby preservingthe waveshape of the signal that would appear if noise were not present.Consequently, the method and apparatus in accordance with the inventionare particularly useful where the incoming alternating electricalcontrol signal is a squarewave pulse train for controlling the operationof digital circuitry.

In accordance with the method aspect of the invention, a method forblanking noise present in an alternating electrical signal is provided.The method preferably comprises the steps of: inputting the alternatingelectrical signal to a first input of a shift register means having aplurality of outputs; inputting clock signals having a preselectedfrequency to a second input of the shift register means for digitallysampling the alternating electrical signal at the times of occurrence ofthe clock signals so as to produce digital samples shiftably stored inrespective storage locations of the shift register means connected tothe plurality of outputs of the shift register means; and inputting thedigital samples appearing at predetermined ones of the plurality ofoutputs of the shift register means to a logic circuit means forproducing a first logic state as an output signal, when a first logicstate appears at the predetermined ones of the plurality of outputs ofthe shift register means, and a second logic state as the output signal,when a second logic state appears at the predetermined ones of theplurality of outputs of the shift register means.

In accordance with the apparatus aspect of the invention, an embodimentis provided for blanking noise present in an alternating electricalsignal. The apparatus preferably comprises: a shift register meanshaving a first input, a second input, a plurality of outputs, andrespective storage locations connected to the plurality of outputs;means for coupling the alternating electrical signal to the first inputof the shift register means; means for coupling clock signals having apreselected frequency to the second input of the shift register means soas to digitally sample the alternating electrical signal at the times ofoccurrence of the clock signals in order to produce digital samplesshiftably stored in the respective storage locations of the shiftregister means; and logic circuit means coupled to predetermined ones ofthe plurality of outputs of the shift register means for producing afirst logic state as an output signal, when a first logic state appearsat the predetermined ones of the plurality of outputs of the shiftregister means, and a second logic state as the output signal, when asecond logic state appears at the predetermined ones of the plurality ofoutputs of the shift register means.

The method and apparatus in accordance with the invention effectivelyeliminate the evidence of noise present in an incoming alternatingelectrical control signal. Consequently, the outgoing electrical controlsignal appears free from noise.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features of the invention and the concomitantadvantages will be better understood and appreciated by those skilled inthe art in view of the description of the preferred embodiments givenbelow in conjunction with the accompanying drawings. In the drawings:

FIG. 1 is a block diagram of a servo control circuit which includes anembodiment in accordance with the invention for blanking noise presentin an alternating electrical signal;

FIG. 2 is a schematic circuit diagram for an implementation of theembodiment shown in FIG. 1 for blanking noise present in an alternatingelectrical signal; and

FIG. 3 illustrates electrical signals which appear at various nodes ofthe circuit shown in FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In accordance with the invention, a method and apparatus are providedfor blanking noise present in an alternating electrical signal. By wayof example, an embodiment of the noise blanking circuit in accordancewith the invention, generally indicated by the numeral 10 in FIG. 1, isincorporated into a servo control circuit 12 for a servomotor 14included in an automated positioning system 16. The servomotor 14 inturn, again by way of example, moves a positionable element 18 in theform of a printing means, such as a print wheel or carriage of a daisywheel printer, via a mechanical link 20 connected to the drive shaft 22of the servomotor.

Movement of the positionable element 18 can be detected by any knowntechnique including the use of a shaft encoder or, alternatively, atachometer. Preferably, as shown in FIG. 1, a shaft encoder 24 includedin the servo control circuit 12 is connected via a mechanical link 26 tothe drive shaft 22 of the servomotor 14. The shaft encoder 24 encodesthe angular position of the drive shaft 22, which is correlated to theactual position of the positionable element 18. Movement of thepositionable element 18 is evidenced by an alternating electricalcontrol output signal produced by the shaft encoder 24.

The circuit of the shaft encoder 24 preferably includes wave shapingcircuitry for filtering the alternating electrical control output signalproduced by the shaft encoder and for converting the shaft encoderoutput signal to a squarewave form, that is, a pulse train comprisingpulses having either a first logic state (low state) or a second logicstate (high state). The filter can comprise a resistor-capacitor filterhaving a time constant which is dependent upon the particular use towhich the servo control circuit 12 shown in FIG. 1 is applied. In thecase where the positionable element 18 is a printing means, for example,the time constant for the filter can be on the order of 40 microseconds,for example.

The output of the shaft encoder 24 is connected by a lead 28 to theinput of the noise blanking circuit 10. The output of the noise blankingcircuit 10 is connected by a lead 30 to a servomotor drive circuit 32which produces a drive signal fed to the servomotor 14 over leads 34.

As mentioned earlier, spurious noise can appear in the alternatingelectrical control output signal from the shaft encoder 24. The outputsignal from the shaft encoder 24 is typically or can be converted to asquarewave pulse train. The pulse train from the shaft encoder 24, whichappears on the lead 28, can have the form shown in FIG. 3A, for example.As shown in FIG. 3A, the pulse train is characterized by being analternating electrical signal comprised of squarewave pulses havingleading edges 36 as represented by amplitude changes of a first givencharacter, for example, positive-going, or rising, amplitude changes.Furthermore, the squarewave pulses have trailing edges 38 as representedby amplitude changes of a second given character, that is,negative-going, or falling, amplitude changes.

As shown in FIG. 3A, noise can be present in the pulse train from theshaft encoder 24 shown in FIG. 1, specifically, noise having anamplitude change of the first given character, that is, a positive-goingamplitude change, as indicated at 40 in FIG. 3A. The noise 40 isrepresented as being similar to a squarewave pulse having a leading edge36 included in the pulse train from the shaft encoder 24 shown inFIG. 1. Also, noise can be present as indicated at 42 in FIG. 3A havingan amplitude change of the second given character, that is, anegative-going amplitude change, which is represented as being similarto a squarewave pulse having a trailing edge 38 included in the pulsetrain from the shaft encoder 24 shown in FIG. 1. The noise blankingcircuit 10 is responsive to the incoming alternating electrical controlsignal in the form of the pulse train from the shaft encoder 24 forblanking the noise 40 and noise 42 shown in FIG. 3A in order to providean outgoing alternating electrical control signal as shown in FIG. 3M inwhich there is no evidence of the noise.

Referring again to FIG. 1, the noise blanking circuit 10 is responsiveto an incoming alternating electrical control signal on the lead 28 fromthe shaft encoder 24, such as the signal shown in FIG. 3A, for detectingnoise present in the signal and producing an outgoing alternatingelectrical control signal on the lead 30 shown in FIG. 1, in whichevidence of the noise 40 and noise 42 shown in FIG. 3A does not appear.An implementation of the noise blanking circuit 10 is shown in FIG. 2.

The noise-laden alternating electrical control signal shown in FIG. 3Afrom the shaft encoder 24 shown in FIG. 1 appears on the lead 28 shownin FIG. 2, which is also designated as node A corresponding to thecircuit location where the signal shown in FIG. 3A appears. As shown inFIG. 2, the lead 28 is connected to a first or serial input (pin 1) of ashift register means 44 (preferably an eight-bit serial-to-parallelshift register type 74164 integrated circuit) included in the noiseblanking circuit 10. Clock signals having a preselected frequency areapplied to a second or clock input (pin 8) of the shift register means44. Preferably, the clock signals are produced by a clock oscillatorcircuit 46 whose output is connected to the clock input of the shiftregister means 44.

The clock signals produced by the clock oscillator circuit 46 preferablyform a pulse train comprised of squarewave pulses having a preselectedfrequency, for example, 187.5 kilohertz (KHz), as shown in FIG. 3B. Theclock signals produced by the clock oscillator circuit 46 shown in FIG.2 preferably have a fifty percent duty cycle, which in the case of apreselected frequency of 187.5 KHz translates to squarewave pulseshaving the logic state (low state) for a period of approximately 2.67microseconds alternating with the second logic state (high state) forthe same period, namely, approximately 2.67 microseconds. Digitalsamples of the incoming alternating electrical control signal shown inFIG. 3A are stored in respective registers or storage locations includedin the shift register means 44 shown in FIG. 2 and are shifted inresponse to the positive-going leading edges of the clock signals.

The serial input of the shift register means 44 comprises one input of atwo-input AND gate. The other input (pin 2) of the two-input AND gateincluded in the shift register means 44 is connected through a pull-upresistor 48 to a second logic state (high state) voltage source, forexample, a regulated +5-volt direct current (DC) power supply.Consequently, the actual logic states which appear at the serial inputof the shift register means 44 are sequentially shifted into the firststorage location of the shift register means at the times of occurrenceof the positive-going leading edges of the clock signals produced by theclock oscillator circuit 46; that is, a first logic state (low state) isshifted into the first storage location of the shift register means uponthe occurrence of a positive-going leading edge of one of the clocksignals, if the incoming alternating electrical control signal whichappears on the lead 28 is at the first logic state (low state) at thetime the positive-going leading edge of the clock signal appears, and,conversely, a second logic state (high state) is shifted into the firststorage location of the shift register means, if the control signal isat the second logic state (high state) at the time the positive-goingleading edge of the clock signal occurs.

A clear input (pin 9) of the shift register means 44 is also connectedto the regulated high state DC power supply through the pull-up resistor48. Consequently, the clear input of the shift register means 44 isdisenabled.

The shift register means 44 includes eight parallel outputs (pins 3, 4,5, 6, 10, 11, 12, and 13) connected to the respective storage locationsincluded in the shift register means. Preferably, as shown in FIG. 2,the parallel output (pin 3), connected to the first storage location ofthe shift register means 44, is connected to a first input of a NANDgate 50 included in the noise blanking circuit 10. Similarly, the thirdparallel output (pin 5), connected to the third storage location of theshift register means 44, is connected to a second input of the NAND gate50. Also, the fifth parallel output (pin 10), connected to the fifthstorage location of the shift register means 44, is connected to a thirdinput of the NAND gate 50. Finally, the eighth parallel output (pin 13),connected to the eighth storage location of the shift register means 44,is connected to a fourth input of the NAND gate 50. The NAND gate 50 canbe a type SN7420 integrated circuit which has only four inputs. Anidentical result can be achieved, however, if an eight-input NAND gatewere available and all eight parallel outputs of the shift registermeans 44 were connected to respective inputs of the eight-input NANDgate.

The output signal produced by the NAND gate 50 assumes the second logicstate (high state) when the first logic state (low state) appears at oneor more of the first, third, fifth, or eighth parallel outputs of theshift register means 44. Conversely, the output signal produced by theNAND gate 50 assumes the first logic state (low state) only when thesecond logic state (high state) appears at all of the first, third,fifth, and eighth parallel outputs of the shift register means 44.

As shown in FIG. 2, the first parallel output, connected to the firststorage location of the shift register means 44, is also connected to afirst input of an inverting NOR circuit 52 included in the noiseblanking circuit 10. Similarly, the third parallel output, connected tothe third storage location of the shift register means 44, is connectedto a second input of the inverting NOR circuit 52. Also, the fifthparallel output, connected to the fifth storage location of the shiftregister means 44, is connected to a third input of the inverting NORcircuit 52. Finally, the eighth parallel output, connected to the eighthstorage location of the shift register means 44, is connected to afourth input of the inverting NOR circuit 52.

The inverting NOR circuit 52 preferably comprises a NOR gate 54, whichcan be a type SN7425 integrated circuit, connected in series with aninverter 56. For the sake of completeness, in the case where the NORgate 54 is implemented by means of a type SN7425 integrated circuit, astrobe input of the NOR gate is connected through a pull-up resistor 58to the regulated high state DC power supply. The type SN7425 integratedcircuit has only four inputs. An identical result can be achieved,however, if an eight-input NOR gate were available and all eightparallel outputs of the shift register means 44 were connected torespective inputs of the eight-input NOR gate.

The output signal produced by the NOR gate 54 assumes the first logicstate (low state) when the second logic state (high state) appears atone or more of the first, third, fifth, or eighth parallel outputs ofthe shift register means 44. Conversely, the output signal produced bythe NOR gate 54 assumes the second logic state (high state) only whenthe first logic state (low state) appears at all of the first, third,fifth, and eighth parallel outputs of the shift register means 44.

The output signal produced by the NOR gate 54 is inverted by theinverter 56. Consequently, the output signal produced by the invertingNOR circuit 52 assumes the second logic state (high state) when thesecond logic state (high state) appears at one or more of the first,third, fifth, and eighth parallel outputs of the shift register means44, and, conversely, the output signal produced by the inverting NORcircuit assumes the first logic state (low state) only when the firstlogic state (low state) appears at all of the first, third, fifth, andeighth parallel outputs of the shift register means.

The output of the NAND gate 50 and the output of the inverting NORcircuit 52 are connected to the inputs of a latch circuit 60 included inthe noise blanking circuit 10. The latch circuit 60 preferably comprisesa pair of cross-coupled NAND gates 62 and 64. The output of the NANDgate 50 is connected to one input of the NAND gate 62, the other inputof the NAND gate 62 being connected to the output of the NAND gate 64.The output of the inverting NOR circuit 52 is connected to one input ofthe NAND gate 64, the other input of the NAND gate 64 being connected tothe output of the NAND gate 62. The output of the latch circuit 60corresponds to the output of the NAND gate 62.

The output signal produced by the latch circuit 60, which corresponds tothe output signal from the noise blanking circuit 10, assumes the firstlogic state (low state) when the output signal from the NAND gate 50 isat the second logic state (high state) and the output signal from theinverting NOR circuit 52 is at the first logic state (low state), whichoccurs only when the first logic state (low state) appears at all of thefirst, third, fifth, and eighth parallel outputs of the shift registermeans 44. Conversely, the output signal produced by the latch circuit60, which corresponds to the output signal from the noise blankingcircuit 10, assumes the second logic state (high state) only when thesecond logic state (high state) appears at all of the first, third,fifth, and eighth parallel outputs of the shift register means 44, whichcauses the output signal from the NAND gate 50 to assume the first logicstate (low state) and the output signal from the inverting NOR circuit52 to assume the second logic state (high state).

Lastly, the output of the latch circuit 60 is connected to the lead 30.As will be described shortly, the noise blanking circuit 10 operates sothat noise having an amplitude change of the first given character,namely, positive-going noise, such as the noise 40 shown in FIG. 3A, andnoise having an amplitude change of the second given character, namely,negative-going noise, such as the noise 42 shown in FIG. 3A, do notappear in the outgoing alternating electrical control signal on the lead30 shown in FIG. 2.

The circuit shown in FIG. 2 is preferably implemented in TTL circuitry.However, different logic circuitry can be used.

The detailed operation of the noise blanking circuit 10 shown in FIG. 2can be facilitated by reference jointly to FIGS. 2 and 3. The incomingalternating electrical control signal shown in FIG. 3A which appears othe lead 28 is input to the serial input of the shift register means 44.

The incoming alternating electrical control signal which appears at theserial input of the shift register means 44 is digitally sampled inresponse to the clock signals which appear at the clock input of theshift register means. The clock signals from the clock oscillatorcircuit 46 at node B shown in FIG. 2 are shown in FIG. 3B. In responseto the positivegoing leading edge of each one of the clock signals shownin FIG. 3B, the logic state, either the first logic state (low state) orthe second logic state (high state), of the incoming alternatingelectrical control signal which appears at the serial input of the shiftregister means 44 is shifted into the first storage location of theshift register means. The logic state of the incoming alternatingelectrical control signal initially shifted into the first storagelocation of the shift register means 44 is subsequently shifted from thefirst storage location to the second storage location of the shiftregister means in response to the next one of the clock signals andthence to the third storage location of the shift register means inresponse to the following clock signal, etc. Subsequently, after beingshifted into the eighth storage location of the shift register means 44,in response to the next one of the clock signals, the logic state of theincoming alternating electrical control signal is shifted out of theshift register means. The output signals which appear at the first,third, fifth, and eighth parallel outputs of the shift register means 44at nodes C, E, G, and J, respectively, shown in FIG. 2 are shown inFIGS. 3C, 3E, 3G, and 3J, respectively.

The digital samples of the incoming alternating electrical controlsignal which appear at the first, third, fifth, and eighth paralleloutputs of the shift register means 44 are input to the NAND gate 50.The output signal produced by the NAND gate 50 at node K shown in FIG. 2is shown in FIG. 3K. The NAND gate 50 produces an output signal havingthe first logic state (low state) only when all of the digital samplesof the incoming alternating electrical control signal which appear atthe first, third, fifth, and eighth parallel outputs of the shiftregister means 44 are at the second logic state (high state).Conversely, if one or more of the digital samples of the incomingalternating electrical control signal stored in the first, third, fifth,and eighth storage locations of the shift register means 44 is at thefirst logic state (low state), the output signal produced by the NANDgate 50 assumes the second logic state (high state).

The digital samples of the incoming alternating electrical controlsignal which appear at the first, third, fifth, and eighth paralleloutputs of the shift register means 44 are also input to the invertingNOR circuit 52. The output signal produced by the inverting NOR circuit52 at node L shown in FIG. 2 is shown in FIG. 3L. The inverting NORcircuit 52 produces an output signal having the first logic state (lowstate) only when all of the digital samples of the incoming alternatingelectrical control signal which appear at the first, third, fifth, andeighth parallel outputs of the shift register means 44 are at the firstlogic state (low state). Conversely, if one or more of the digitalsamples of the incoming alternating electrical control signal stored inthe first, third, fifth, and eighth storage locations of the shiftregister means 44 is at the second logic state (high state), the outputsignal produced by the inverting NOR circuit 52 assumes the second logicstate (high state).

The output signals from the NAND gate 50 and the inverting NOR circuit52 are input to the latch circuit 60. The output signal produced by thelatch circuit 60 at node M shown in FIG. 2, which corresponds to theoutput signal from the noise blanking circuit 10, is shown in FIG. 3M.The latch circuit 60 produces an output signal which transposes to thesecond logic state (high state) when all of the digital samples of theincoming alternating electrical control signal stored in the first,third, fifth, and eighth storage locations of the shift register means44 are at the second logic state (high state). Conversely, the outputsignal produced by the latch circuit 60 transposes to the first logicstate (low state) when all of the digital samples of the incomingalternating electrical control signal stored in the first, third, fifth,and eighth storage locations of the shift register means 44 are at thefirst logic state (low state).

Digital sampling of the incoming alternating electrical control signalshown in FIG. 3A which appears at the serial input of the shift registermeans 44 in response to the clock signals shown in FIG. 3B produces theoutput signals shown in FIGS. 3C through 3J at the parallel outputs ofthe shift register means. Although only the output signals shown inFIGS. 3C, 3E, 3G, and 3J which appear at the first, third, fifth, andeighth parallel outputs of the shift register means 44 affect theoperation of the noise blanking circuit 10 shown in FIG. 2, the outputsignals which appear at all eight parallel outputs of the shift registermeans are shown in FIG. 3 for the sake of completeness.

As shown in FIGS. 3A through 3C, the logic states of the incomingalternating electrical control signal shown in FIG. 3A at the times ofoccurrence of the positive-going leading edges 66 of the clock signalsshown in FIG. 3B are sequentially shifted into the first storagelocation of the shift register means 44 as represented by the outputsignal from the first storage location of the shift register means shownin FIG. 3C. Considered in further detail, the logic state of theincoming alternating electrical control signal shown in FIG. 3A is atthe first logic state (low state) at the times of occurrence of thepositive-going leading edges of the initial two clock signals shown inFIG. 3B. Upon the occurrence of the positive-going leading edge of thethird one of the clock signals shown in FIG. 3B, however, the logicstate of the incoming alternating electrical control signal shown inFIG. 3A is at the second logic state (high state). Consequently, thedigital sample shifted into the first storage location of the shiftregister means 44 is at the second logic state (high state).

The incoming alternating electrical control signal shown in FIG. 3Aremains at the second logic state (high state) until the occurrence ofthe noise 42 shown in FIG. 3A. As a consequence of the noise 42, digitalsampling of the incoming alternating electrical control signal shown inFIG. 3A at the times of occurrence of the positive-going leading edgesof clock signals 68 and 70 shown in FIG. 3B causes the digital samplessequentially shifted into the first storage location of the shiftregister means 44 to be at the first logic state (low state) as shown at72 in FIG. 3C. Subsequently, upon the dissipation of the noise 42 andthe consequent return of the incoming alternating electrical controlsignal shown in FIG. 3A to the second logic state (high state), thedigital samples sequentially shifted into the first storage location ofthe shift register means 44 are again at the second logic state (highstate) as shown at 74 in FIG. 3C.

The logic state of the incoming alternating electrical control signalshown in FIG. 3A is at the first logic state (low state) at the times ofoccurrence of the positive-going leading edges of clock signals 76 and78 shown in FIG. 3B. Consequently, the digital samples of the incomingalternating electrical control signal sequentially shifted into thefirst storage location of the shift register means 44 are at the firstlogic state (low state).

The incoming alternating electrical control signal shown in FIG. 3Aremains at the first logic state (low state) until the occurrence of thenoise 40 shown in FIG. 3A. As a consequence of the noise 40, digitalsampling of the incoming alternating electrical control signal shown inFIG. 3A at the times of occurrence of the positive-going leading edgesof clock signals 80 and 82 shown in FIG. 3B causes the digital samplessequentially shifted into the first storage location of the shiftregister means 44 to be at the second logic state (high state) as shownat 84 in FIG. 3C. Subsequently, upon the dissipation of the noise 40 andthe consequent return of the incoming alternating electrical controlsignal shown in FIG. 3A to the first logic state (low state), thedigital samples sequentially shifted into the first storage location ofthe shift register means 44 are again at the first logic state (lowstate) as shown at 86 in FIG. 3C.

FIGS. 3C through 3J show that the digital samples of the incomingalternating electrical control signal at the times of occurrence of thepositive-going leading edges of the clock signals shown in FIG. 3B aresequentially shifted from one storage location to the next and finallyout of the shift register means 44. The difference between the outputsignals which appear at the parallel outputs of the shift register means44 shown in FIGS. 3C through 3J are the phases of the respectivesignals. The output signals which appear at all of the storage locationsof the shift register means 44, which is preferably an eight-bit shiftregister, are shown in FIGS. 3C through 3J in order to better illustratethe phase differences.

The output signals shown in FIGS. 3C, 3E, 3G, and 3J which appear at thefirst, third, fifth, and eighth parallel outputs of the shift registermeans 44 are input to the NAND gate 50 which produces the output signalshown in FIG. 3K. In response to the signals shown in FIGS. 3C, 3E, 3G,and 3J stored in the first, third, fifth, and eighth storage locationsof the shift register means 44, the NAND gate 50 produces an outputsignal having the second logic state (high state) when one or more ofthe output signals from the first, third, fifth, and eighth storagelocations of the shift register means is at the first logic state (lowstate) as shown at 88 in FIG. 3K. When all of the signals shown in FIGS.3C, 3E, 3G, and 3J which appear at the first, third, fifth, and eighthparallel outputs of the shift register means 44 are at the second logicstate (high state), however, the output signal produced by the NAND gate50 transposes to the first logic state (low state) as shown at 90 inFIG. 3K. As a consequence of the operation of the shift register means44 in response to the noise 42 and the logical combination of the outputsignals from the shift register means by means of the NAND gate 50,there is no evidence of the noise 42 in the output signal produced bythe latch circuit 60, as indicated by a comparison of the noise-ladenincoming alternating electrical control signal shown in FIG. 3A with theoutput signal produced by the latch circuit, which corresponds to theoutput signal from the noise blanking circuit 10, shown in FIG. 3M.

The signals shown in FIGS. 3C, 3E, 3G, and 3J which appear at the first,third, fifth, and eighth parallel outputs of the shift register means 44are also input to the inverting NOR circuit 52 which produces the outputsignal shown in FIG. 3L. In response to the signals shown in FIGS. 3C,3E, 3G, and 3J stored in the first, third, fifth, and eighth storagelocations of the shift register means 44, the inverting NOR circuit 52produces an output signal having the second logic state (high state)when one or more of the output signals from the first, third, fifth, andeighth storage locations of the shift register means is at the secondlogic state (high state) as shown at 92 in FIG. 3L. When all of thesignals shown in FIGS. 3C, 3E, 3G, and 3J which appear at the first,third, fifth, and eighth parallel outputs of the shift register means 44are at the first logic state (low state), however, the output signalproduced by the inverting NOR circuit 52 transposes to the first logicstate (low state) as shown at 94 in FIG. 3L. Evidence of the noise 40 isnot present in the output signal from the latch circuit 60 as aconsequence of the operation of the shift register means 44 in responseto the noise 40 and the logical combination of the output signals fromthe shift register means by means of the inverting NOR circuit 52, asindicated by a comparison of the noise-laden incoming alternatingelectrical control signal shown in FIG. 3A with the output signalproduced by the latch circuit, which corresponds to the output signalfrom the noise blanking circuit 10, shown in FIG. 3M.

The output signal produced by the NAND gate 50 shown in FIG. 3K and theoutput signal produced by the inverting NOR circuit 52 shown in FIG. 3Lare input to the latch circuit 60. The latch circuit 60 produces anoutput signal having the first logic state (low state) until such timeas the digital samples of the incoming alternating electrical controlsignal which appear at the first, third, fifth, and eighth paralleloutputs of the shift register means 44 all transpose to the second logicstate (high state), whereupon the output signal produced by the NANDgate 50 transposes from the second logic state (high state) to the firstlogic state (low state), which causes the output signal produced by thelatch circuit to transpose from the first logic state (low state) to thesecond logic state (high state) as shown at 96 in FIG. 3M. As shown inFIG. 3M, the output signal produced by the latch circuit 60 remains atthe second logic state (high state) until such time as the digitalsamples of the incoming alternating electrical control signal stored inthe first, third, fifth, and eighth storage locations of the shiftregister means 44 all transpose to the first logic state (low state),whereupon the output signal produced by the inverting NOR circuit 52transposes from the second logic state (high state) to the first logicstate (low state), which causes the output signal produced by the latchcircuit to transpose from the second logic state (high state) to thefirst logic state (low state) as shown at 98 in FIG. 3M.

The output signal from the latch circuit 60 appears at node M shown inFIG. 2 and is shown in FIG. 3M and comprises the logical combination ofthe output signal from the NAND gate 50 and the output signal from theinverting NOR circuit 52 for blanking the noise 40 and noise 42 in theincoming alternating electrical control signal shown in FIG. 3A. Theoutput signal from the latch circuit 60 provides an outgoing alternatingelectrical control signal in which evidence of the noise 40 and noise 42is eliminated at the node M shown in FIG. 2, which corresponds to thelead 30.

In summary, when what appears to be a transposition to the second logicstate (high state), indicated by what appears to be a leading edge 36 ofthe incoming alternating electrical control signal, is detected, adigital sampling means in the form of the shift register means 44 storessamples at preselected internals, for example, at intervals of 5.33microseconds. If the transposition to the second logic state (highstate) does not persist for at least a predetermined period, forexample, a 40-microsecond period, the positive-going electrical signalis considered to be noise. If the second logic state (high state)persists for at least the predetermined period, the positive-goingelectrical signal is considered to be a valid pulse. This conditioncontinues until what appears to be a transposition to the first logicstate (low state) indicated by a trailing edge 38 of the incomingalternating electrical control signal is sensed.

Similar to the case of detection of a valid positive-going electricalsignal, when what appears to be a transposition to the first logic state(low state), indicated by what appears to be a trailing edge 38 of theincoming alternating electrical control signal, is detected, the digitalsampling means in the form of the shift register means 44 storessamples, preferably at intervals of 5.33 microseconds. If thetransposition to the first logic state (low state) does not persist forat least the predetermined period, the negative-going electrical signalis considered to be noise. If the first logic state (low state) persistsfor at least the predetermined period, the negative-going electricalsignal is considered to be a valid pulse.

Preferably, the preselected period of the clock signals is 5.33microseconds. The period of the clock signals can, however, be otherthan 5.33 microseconds. In the case where the noise blanking circuit 10is incorporated into the servo control circuit 12 shown in FIG. 1, theperiod of the clock signals is preferably keyed to the slew rate for theservomotor 14. The slew rate for the servomotor 14, for example, can be250 microseconds. The choice of 5.33 microseconds is based on theselection of 40 microseconds, which is approximately one-sixth of theslew period, as the maximum expected noise duration (i.e., electricalsignals which do not persist for at least 40 microseconds are rejectedas noise). The selection of 40 microseconds assures that valid pulses inthe incoming alternating electrical control signal are not missed. Theselection of 5.33 microseconds as the period of the clock signals isthen based on the implementation of the shift register means 44 includedin the embodiment shown in FIG. 2 by means of an eight-bit shiftregister, such that the selected clock signal period (5.33 microseconds)times the number of storage locations included in the shift register(eight) approximately equals the maximum expected noise duration(approximately 40 microseconds). Therefore, the selectivity of the noiseblanking circuit 10, that is, the noise rejection characteristic of thenoise blanking circuit, can be selected by adjusting the clock signalperiod and/or number of storage locations included in the shift registermeans 44. Also, for a given shift register means 44, changing theconnections of the parallel outputs, connected to the storage locationsof the shift register means, to the inputs of the NAND gate 50 andinverting NOR circuit 52 can produce an identical result to adjustingthe number of storage locations included in the shift register means forselecting the noise rejection characteristic of the noise blankingcircuit 10.

Although one implementation of the noise blanking circuit 10 is shown inFIG. 2, the apparatus for blanking noise present in an alternatingelectrical control signal in accordance with the invention can beimplemented by other means, namely, a microprocessor circuit having aset of programmed instructions stored in a read only memory included inthe microprocessor. A microprocessor circuit can be programmed fordigitally sampling the incoming alternating electrical control signal asperformed by the shift register means 44 and logically combining thedigital samples as performed by the NAND gate 50, inverting NOR circuit52, and latch circuit 60 for producing an outgoing alternatingelectrical control signal in which evidence of the noise 40 and noise 42shown in FIG. 3A is eliminated. The circuit shown in FIG. 2 is, however,preferred since a microprocessor circuit can be more complex and costly.

In actual tests conducted, the noise blanking circuit in accordance withthe invention has enabled error free operation of extremely noisyservomechanisms in daisy wheel printers. Consequently, the method andapparatus in accordance with the invention solve the problem of noise inthe shaft encoder or tachometer signals causing erroneous interpretationof the operation of the print wheel and carriage. As a result, thequality of printing is improved and damage to or breakage of the printwheel is avoided.

While various embodiments of a noise blanking circuit have beendescribed in order to make the invention understandable to those skilledin the art, it will be appreciated that modifications not mentioned willbecome apparent to those skilled in the art. It is to be clearlyunderstood that the above description is by way of example andillustration only and is not to be taken by way of limitation.Accordingly, the spirit and scope of this invention are ascertainableonly by reference to the appended claims.

What is claimed is:
 1. A method for blanking noise present in analternating electrical signal correlated to movement of a positionableelement in an automated positioning system, comprising the stepsof:inputting the alternating electrical signal to a first input of ashift register means having a plurality of outputs; inputting clocksignals having a preselected frequency to a second input of the shiftregister means for digitally sampling the alternating electrical signalat the times of occurrence of the clock signals so as to produce digitalsamples shiftably stored in respective storage locations of the shiftregister means connected to the plurality of outputs of the shiftregister means; inputting the digital samples appearing at predeterminedones of the plurality of outputs of the shift register means to a logiccircuit means for producing a first logic state as an output signal,when a first logic state appears at the predetermined ones of theplurality of outputs of the shift register means, and a second logicstate as the output signal, when a second logic state appears at thepredetermined ones of the plurality of outputs of the shift registermeans; and outputting the output signal produced by the logic circuitmeans as an outgoing alternating electrical control signal correlated tomovement of the positionable element; whereby the noise does not appearin the outgoing alternating electrical control signal.
 2. The method ofclaim 1 wherein the frequency of the clock signals is preselected fordetermining a selected noise rejection characteristic.
 3. The method ofclaim 1 wherein the number of storage locations of the shift registermeans is preselected for determining a selected noise rejectioncharacteristic.
 4. The method of claim 1 wherein the frequency of theclock signals and the number of storage locations of the shift registermeans are preselected for determining a selected noise rejectioncharacteristic.
 5. The method of claim 1 wherein the predetermined onesof the plurality of outputs of the shift register means connected to thelogic circuit means are preselected for determining a selected noiserejection characteristic.
 6. A method for blanking noise present in analternating electrical signal, comprising the steps of:inputting thealternating electrical signal to a serial input of a shift registermeans having a plurality of parallel outputs; inputting clock signalshaving a preselected frequency to a clock input of the shift registermeans for digitally sampling the alternating electrical signal at thepreselected frequency, the logic states of the alternating electricalsignal at the times of occurrence of the clock signals being shiftablystored in respective storage locations of the shift register meansconnected to the plurality of parallel outputs of the shift registermeans; inputting the logic states appearing at predetermined ones of theplurality of parallel outputs of the shift register means to a firstlogic circuit means for producing a first logic state as an outputsignal from the first logic circuit means when a second logic stateappears at the predetermined ones of the plurality of parallel outputsof the shift register means, the second logic state being produced asthe output signal from the first logic circuit means when the firstlogic state appears at any of the predetermined ones of the plurality ofparallel outputs of the shift register means; inputting the logic statesappearing at the predetermined ones of the plurality of parallel outputsof the shift register means to a second logic circuit means forproducing the first logic state as an output signal from the secondlogic circuit means when the first logic state appears at thepredetermined ones of the plurality of parallel outputs of the shiftregister means, the second logic state being produced as the outputsignal from the second logic circuit means when the second logic stateappears at any of the predetermined ones of the plurality of paralleloutputs of the shift register means; and inputting the output signalsfrom the first and second logic circuit means to a latch circuit meansfor producing the first logic state as an output signal from the latchcircuit means, when the output signal from the second logic circuitmeans transposes to the first logic state, and the second logic state asthe output signal from the latch circuit means, when the output signalfrom the first logic circuit means transposes to the first logic state.7. The method of claim 6 wherein the frequency of the clock signals ispreselected for determining a selected noise rejection characteristic.8. The method of claim 6 wherein the number of storage locations of theshift register means is preselected for determining a selected noiserejection characteristic.
 9. The method of claim 6 wherein the frequencyof the clock signals and the number of storage locations of the shiftregister means are preselected for determining a selected noiserejection characteristic.
 10. The method of claim 6 wherein thepredetermined ones of the plurality of parallel oututs of the shiftregister means connected to the first and second logic circuit means arepreselected for determining a selected noise rejection characteristic.11. A method for blanking noise present in an alternating electricalsignal, comprising the steps of:generating clock signals at apreselected frequency; inputting the alternating electrical signal to aserial input of a serial-to-parallel shift register having a pluralityof parallel outputs; inputting the clock signals to a clock input of theshift register for digitally sampling the alternating electrical signalat the preselected frequency, the logic states of the alternatingelectrical signal at the times of occurrence of the clock signals beingshiftably stored in respective storage locations of the shift register,the respective storage locations of the shift register being connectedto the plurality of parallel outputs of the shift register; inputtingthe logic states appearing at predetermined ones of the plurality ofparallel outputs of the shift register to a NAND gate circuit forproducing a low logic state as an output signal from the NAND gatecircuit when a high logic state appears at the predetermined ones of theplurality of parallel outputs of the shift register, the high logicstate being produced as the output signal from the NAND gate circuitwhen the low logic state appears at any of the predetermined ones of theplurality of parallel outputs of the shift register; inputting the logicstates appearing at the predetermined ones of the plurality of paralleloutputs of the shift register to an inverting NOR circuit for producingthe low logic state as an output signal from the inverting NOR circuitwhen the low logic state appears at the predetermined ones of theplurality of parallel outputs of the shift register, the high logicstate being produced as the output signal from the inverting NOR circuitwhen the high logic state appears at any of the predetermined ones ofthe plurality of parallel outputs of the shift register; and inputtingthe output signals from the NAND gate circuit and inverting NOR circuitto a latch circuit for producing the low logic state as an output signalfrom the latch circuit, when the output signal from the inverting NORcircuit transposes to the low logic state, and the high logic state asthe output signal from the latch circuit, when the output signal fromthe NAND gate circuit transposes to the low logic state.
 12. The methodof claim 11 wherein the frequency of the clock signals is preselectedfor determining a selected noise rejection characteristic.
 13. Themethod of claim 11 wherein the number of storage locations of the shiftregister is preselected for determining a selected noise rejectioncharacteristic.
 14. The method of claim 11 wherein the frequency of theclock signals and the number of storage locations of the shift registerare preselected for determining a selected noise rejectioncharacteristic.
 15. The method of claim 11 wherein the predeterminedones of the plurality of parallel outputs of the shift registerconnected to the NAND gate circuit and the inverting NOR circuit arepreselected for determining a selected noise rejection characteristic.16. Apparatus for blanking noise present in an alternating electricalsignal correlated to movement of a positionable element in an automatedpositioning system, comprising:a shift register means having a firstinput, a second input, a plurality of outputs, and respective storagelocations connected to the plurality of outputs; means for coupling thealternating electrical signal to the first input of the shift registermeans; means for coupling clock signals having a preselected frequencyto the second input of the shift register means so as to digitallysample the alternating electrical signal at the times of occurrence ofthe clock signals in order to produce digital samples shiftably storedin the respective storage locations of the shift register means; andlogic circuit means coupled to predetermined ones of the plurality ofoutputs of the shift register means for producing a first logic state asan output signal, when a first logic state appears at the predeterminedones of the plurality of outputs of the shift register means, and asecond logic state as the output signal, when a second logic stateappears at the predetermined ones of the plurality of outputs of theshift register means; the output signal produced by the logic circuitmeans being utilized as an outgoing alternating electrical controlsignal correlated to movement of the positionable element, in whichthere is no evidence of the noise.
 17. The apparatus of claim 16,further comprising a shaft encoder means mechanically connected to thepositionable element for producing the alternating electrical signal inresponse to movement of the positionable element.
 18. The apparatus ofclaim 17, further comprising wave shaping circuitry included in theshaft encoder means for filtering the alternating electrical signal andfor converting the alternating electrical signal to a squarewave form.19. Apparatus for blanking noise present in an alternating electricalsingal, comprising:a shift register means having a serial input, a clockinput, a plurality of parallel outputs, and respective storage locationsconnected to the plurality of parallel outputs; means for coupling thealternating electrical signal to the serial input of the shift register;means for coupling clock signals having a preselected frequency to theclock input of the shift register means so as to digitally sample thealternating electrical signal at the preselected frequency, the logicstates of the alternating electrical signal at the times of occurrenceof the clock signals being shiftably stored in the respective storagelocations of the shift register means connected to the plurality ofparallel outputs of the shift register means; a first logic circuitmeans coupled to predetermined ones of the plurality of parallel outputsof the shift register means for producing a first logic state as anoutput signal from the first logic circuit means when a second logicstate appears at the predetermined ones of the plurality of paralleloutputs of the shift register means, the second logic state beingproduced as the output signal from the first logic circuit means whenthe first logic state appears at any of the predetermined ones of theplurality of parallel outputs of the shift register means; a secondlogic circuit means coupled to the predetermined ones of the pluralityof parallel outputs of the shift register means for producing the firstlogic state as an output signal from the second logic circuit means whenthe first logic state appears at the predetermined ones of the pluralityof parallel outputs of the shift register means, the second logic statebeing produced as the output signal from the second logic circuit meanswhen the second logic state appears at any of the predetermined ones ofthe plurality of parallel outputs of the shift register means; and alatch circuit means coupled to the first and second logic circuit meansfor producing the first logic state as an output signal from the latchcircuit means, when the output signal from the second logic circuitmeans transposes to the first logic state, and the second logic state asthe output signal from the latch circuit means, when the output signalfrom the first logic circuit means transposes to the first logic state.20. Apparatus for blanking noise present in an alternating electricalsignal, comprising:means for generating clock signals at a preselectedfrequency; a serial-to-parallel shift register having a serial input, aclock input, a plurality of parallel outputs, and respective storagelocations connected to the plurality of parallel outputs; means forcoupling the alternating electrical signal to the serial input of theshift register; means for coupling the clock signals to the clock inputof the shift register so as to digitally sample the alternatingelectrical signal at the preselected frequency, the logic states of thealternating electrical signal at the times of occurrence of the clocksignals being shiftably stored in the respective storage locations ofthe shift register, the respective storage locations of the shiftregister being connected to the plurality of parallel outputs of theshift register; a NAND gate circuit coupled to predetermined ones of theplurality of parallel outputs of the shift register for producing a lowlogic state as an output signal from the NAND gate circuit when a highlogic state appears at the predetermined ones of the plurality ofparallel outputs of the shift register, the high logic state beingproduced as the output signal from the NAND gate circuit when the lowlogic state appears at any of the predetermined ones of the plurality ofparallel outputs of the shift register; an inverting NOR circuit coupledto the predetermined ones of the plurality of parallel outputs of theshift register for producing the low logic state as an output signalfrom the inverting NOR circuit when the low logic state appears at thepredetermined ones of the plurality of parallel outputs of the shiftregister, the high logic state being produced as the output signal fromthe inverting NOR circuit when the high logic state appears at any ofthe predetermined ones of the plurality of parallel outputs of the shiftregister; and a latch circuit coupled to the NAND gate circuit andinverting NOR circuit for producing the low logic state as an outputsignal from the latch circuit, when the output signal from the invertingNOR circuit transposes to the low logic state, and the high logic stateas the output signal from the latch circuit, when the output signal fromthe NAND gate circuit transposes to the low logic state.